1. Field of the Invention
The present invention relates to a frequency divider and a method for controlling the frequency divider. The present invention relates to a frequency divider, for example, for use in radio communication apparatuses such as cellular phones, and a method for controlling the frequency divider.
2. Related Art of the Invention
In recent years, radio communication systems have been commonly used in public communications, computer networks, and the like. Further, the use of a system has been started which has a reduced number of oscillators for a reduction in the size and cost of high frequency ICs, and frequency dividers connected behind the oscillators and having different frequency dividing ratios in order to deal with a plurality of transmission frequencies.
Some conventional techniques implement switching of the frequency dividing ratio by connecting a plurality of frequency division circuits in series and switching a path for output signals (see, for example, Patent Document 1: Japanese Patent Laid-Open No. 63-18721 (for example, FIG. 1)).
FIG. 8 shows a circuit diagram illustrating the basic concept of the conventional frequency divider described in Patent Document 1.
The circuit is configured so that a first frequency dividing circuit 81 and a second frequency dividing circuit 82 are connected together in series so as to allow an output from the frequency dividing circuits to be output as a frequency dividing signal via a switching circuit 83. The first frequency dividing circuit 81 divides the frequency of an input signal by M and outputs the resulting signals. The signals obtained by the first frequency dividing circuit 81 by dividing the frequency of the input signal by M are input to the second frequency dividing circuit 82, which further divides the frequency of each of the signals by N and outputs the resulting signals.
As shown by a solid line in the switching circuit 83 in FIG. 8, if the output of the second frequency dividing circuit 82 is connected to an output terminal 85, the output terminals 85 outputs an output signal of the second frequency dividing circuit 82, that is, Vb obtained by dividing an input signal from an input terminal 84 by (M×N).
To obtain an output signal Va with a frequency dividing ratio different from that of the output signal Vb while the output signal Vb is being output from the output terminal 85 as described above, a control signal Vc switches the connection in the switching circuit 83 as shown by a dotted line, while simultaneously blocking a current source for the second frequency dividing circuit 82.
Thus switching the connection in the switching circuit 83 makes the frequency dividing circuit 82 inoperative and simultaneously reduces power consumption. That is, the control signal Vc serves both as a switching control signal and as a power supply blocking control signal. A given timing correlation can be considered to be simultaneous.
The output signals Va output by the first frequency dividing circuit 81 and obtained by dividing the frequency of the input signal by M are output from the output terminal 85 via the switching circuit 83.
In the prior art, connection paths to the plurality of frequency dividing circuits are switched to allow the output signals Va and Vb with the different frequency dividing ratios to be output.
Further, in a similar configuration, a fixed frequency divider or a variable frequency divider is provided by providing a switch function between the output and input of a master slave flip flop so as to vary the number of stages of a feedback loop (see, for example, Patent Document 2: Japanese Patent Laid-Open No. 63-244931 (for example, FIG. 1)).
FIG. 9 shows a circuit diagram of the frequency divider described in Patent Document 2.
Three master slave flip flops 91, 92, 93 are connected in series. A switch 90 switches connection paths to the flip flops 91, 92, 93. Each of the master slave flip flops 91, 92, 93 is a frequency dividing circuit that divides the frequency of an input signal by two and outputs the resulting signals.
An OR gate 94 generates a signal from both an output signal from the master slave flip flop 92 and a control signal 95, and this signal switches the connection in the switch 90.
As shown by a solid line in the switch 90 in FIG. 9, if connections are made so that an output from the master slave flip flop 93 is input to the master slave flip flop 92, the configuration of the master slave flip flops 92 and 93 serves to divide the frequency of a clock signal by four and to output the resulting signals.
With the master slave flip flops 92 and 93 thus connected, switching the connection in the switch 90 as shown by a dotted line causes an output from the master slave flip flop 91 to be input to the master slave flip flop 92. In this case, the configuration of the master slave flip flops 91, 92, and 93 serves to divide the frequency of a clock signal by eight and to output the resulting signals.
As described above, also with the frequency divider described in Patent Document 2, the path between the plurality of frequency dividing circuits is switched to allow a plurality of output signals with different frequency dividing ratios to be output.